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rail- to - rail, fast, low power 2.5 v to 5.5 v, single - supply ttl/cmos comparator data sheet adcmp609 features fully specified rail - to - rail at v cc = 2.5 v to 5.5 v input common - mode voltage from ?0.2 v to v cc + 0.2 v low glitch ttl - / cmos - c ompatible output stage 4 0 ns propagation delay low power 1 mw at 2.5 v shutdown pin p rogrammable hysteresis power su ppl y rejection > 6 0 db ? 40c to +125 c operation applications high speed instrumentation clock and data signal restoration logic level shifting or translation high speed line receivers threshold detection peak and zero - crossing detectors high speed trigger ci rcuitry pulse - width modulators current/voltage controlled oscillators functional block dia gram 06918-001 adcmp609 noninverting input inverting input q output + ? s dn figure 1 . general description th e adcmp609 is a fast comparator fabricated on xfcb2 , an analog devices, inc. , proprietary process. th ese comparator s are exceptionally versatile and easy to use. features include an input range from v ee ? 0.2 v to v cc + 0.2 v, low noise , ttl - / cmos - compatible output drivers, and adjustable hysteresis and/or shutdown input s. the device offer s 4 0 ns propagation delay driving a 15 pf load with 10 mv overdrive on 5 00 a typical supply current. a flexible power supply scheme allows the device s to operate with a single +2.5 v positive supply and a ? 0.2 v to +3.0 v input signal range up to a +5 .5 v positive supply with a ? 0.2 v to +5.7 v input signal range. the ttl - /cmos - compatible output stage is designed to dri ve up to 1 5 pf with full rated timing specifications and to degrade in a graceful and linear fashion as additional capacitance is added. the input stage of the comparator offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. a programmable hysteresis feature is also provided. the adcmp609 , available in an 8 - lead msop packag e, features a shutdown pin and h yste resis control . rev. c d ocument feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result fr om its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one tec hnology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2007C 2014 analog devices, inc. all rights reserved. technical sup port www.analog.com
adcmp609 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 function al block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 spec ifications ..................................................................................... 3 electrical characteristics ............................................................. 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 applications information .................................................................8 power/ground layout and bypassing ........................................8 ttl - /cmos - compatible output stage ....................................8 optimizing performance ..............................................................8 comparat or propagation delay dispersion ..................................8 comparator hysteresis .................................................................9 crossover bias point .....................................................................9 minimum input slew rate requirement ................................ 10 typical applications circuits ........................................................ 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 11 /14 rev. b to rev. c change to figure 9 and figure 10 .................................................. 7 6/14 rev. a to rev. b added storage temperature range of ? 65 c to +1 5 0 c ............ 4 update d outline dimensions ....................................................... 12 8 /08 rev. 0 to rev. a changes to table 4 ............................................................................ 5 changes to ordering guide .......................................................... 12 7/0 7 revision 0: initial versi on rev. c | page 2 of 12
data sheet adcmp609 specifications electrical character istics v cc = 2.5 v, t a = ?40 c to + 125c ; t ypical value is t a = 25c, unless otherwise n oted. table 1. parameter symbol conditions min typ max unit dc input characteristics voltage range v p , v n v cc = 2.5 v to 5.5 v ? 0.2 v cc + 0.2 v v common - mode range v cc = 2.5 v to 5.5 v ?0.2 v cc + 0.2 v v differential vo ltage v cc = 2.5 v to 5.5 v v cc v offset voltage v os ?5.0 3 +5.0 mv bias current i p , i n ? 0.4 +0.4 a offset current ? 1.0 +1.0 a capacitance c p , c n 1 pf resistance, differential mode ?0.5 v to v cc + 0.5 v 200 7000 k? resistance, common mode ?0.5 v to v cc + 0.5 v 100 4000 k ? active gain a v 80 db common - mode rejection ratio cmrr v cc = 2.5 v 50 db v cm = ? 0.2 v to +2.7 v v cc = 5.5 v 50 db hysteresis r hys = 0.1 mv hysteresis mode and timing hysteresis mode b ias voltage current ? 1 a 1.145 1.25 1.35 v minimum resi stor value hysteresis = 120 mv 30 120 k? shutdown pin characteristics 1 v ih comparator is operating 2.0 v cc v v il shutdown guaranteed ? 0.2 +0.4 +0.4 v i ih v ih = v cc ? 6 +6 a sleep time t sd l cc < 100 a 300 ns wake - up time t h v pp = 10 mv, output valid 150 ns dc output characteristics v cc = 2.5 v to 5.5 v output voltage high level v oh i oh = 0.8 ma, v cc = 2.5 v v cc ? 0.4 v output voltage low level v ol i ol = 0.8 ma, v cc = 2.5 v 0.4 v ac performance 2 v cc = 2.5 v to 5.5 v rise time/fall time t r /t f 10% to 90%, v cc = 2.5 v 25 to 50 ns 10% to 90%, v cc = 5.5 v 45 to 75 ns propagation delay t pd v od = 10 mv, v cc = 2.5 v 30 to 50 ns v od = 50 mv, v cc = 5.5 v 35 to 60 ns p ropagation delay skew , rising to falling transition v cc = 2.5 v 4.5 ns v cc = 5.5 v 8 ns propag ation delay skew , q to q v cc = 2.5 v 3 ns v cc = 5.5 v 4 ns overdrive dispersion 10 mv < v od < 125 mv 12 ns common - mode dispersion ? 0.2 v < v cm < v cc + 0.2 v 1.5 ns power supply supply voltage range v cc 2.5 5.5 v positive supply current i vcc v cc = 2.5 v 550 650 a v cc = 5.5 v 800 1100 a power dissipation p d v cc = 2.5 v 1.4 1.7 mw v c c = 5.5 v 4.5 7 mw power supply rejection ratio psrr v cc = 2.5 v to 5.5 v ?50 db shutdown current i sd v cc = 2.5 v to 5.5 v 150 260 a 1 the output is a high impedance mode when the device is in shutdown mode. note that this feature is to be used with care since the enable/disable time is much longer than with a true tristate output . 2 v in = 100 mv square input at 1 mhz, v cm = 0 v, c l = 15 pf, v cci = 2.5 v, unless otherwise noted. rev. c | page 3 of 12
adcmp609 data sheet absolute maximum rat ings table 2. parameter rating supply voltages supply voltage (v cc to ground) ? 0.5 v to +6.0 v supply differential ? 6.0 v to +6.0 v input voltages input voltage ? 0.5 v to v cc + 0.5 v differential input voltage (v cc + 0.5 v) maximum input/output current 50 ma shutdown pin applied voltage (s dn to ground) ? 0.5 v to v cc + 0.5 v maximum input/output current 50 ma hysteresis control pin applied voltage (hys to ground) ? 0.5 v to v cc + 0.5 v maximum input/output current 50 ma output current 50 ma operating temperature ambient temperature range ? 40c to + 125c junction temperature 150c storage temperature range ?65 c to +150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3. package type ja 1 unit adcmp609 8- lead msop 130 c/ w 1 measurement in still air. esd caution rev. c | page 4 of 12
data sheet adcmp609 pin configuration an d function descripti ons adcmp609 top view (not to scale) v cc 1 q 8 v p 2 q 7 v n 3 v ee 6 s dn 4 hys 5 06918-002 figure 2 . adcmp609 pin configuration table 4. adcmp609 pin function descriptions pin no. mnemonic description 1 v cc v cc supply. 2 v p noninverting analog input. 3 v n inverting analog input. 4 s dn shutdown. drive this pin low to shut down the device. 5 h ys hysteresis control. bias with resistor or current source for hysteresis. 6 v ee negative supply voltage. 7 q noninv erting output. q is at logic high if the analog voltage at the noninverting input ( v p ) is greater than the analog voltage at the invertin g input ( v n ) , provided the comparator is in compare mode. 8 q inverting output. q is at logic low if the analog voltage at the noninverting input ( v p ) is greater than the analog voltage at the inverting input ( v n ) , provided the comparator is in comp are mode. rev. c | page 5 of 12
adcmp609 data sheet typical performance characteristics v cc = 2.5 v, t a = 25c, unless otherwise noted. 06918-003 7 6 5 4 3 2 1 0 ? 1 h ys p i n v o l t a g e ( v ) 4 0 0 3 0 0 2 0 0 1 0 0 0 ?10 0 ?20 0 ?30 0 ?40 0 cur r e n t ( a ) v cc = 2.5v v cc = 5.5v figure 3 . hys p in current (a) v s . v oltage (v) 06918-004 3 . 5 3 . 0 2 . 5 2 . 0 1 . 5 1 . 0 0 . 5 0 ?0 . 5 ?1 . 0 5 4 3 2 1 0 ? 1 ? 2 ? 3 ? 4 ? 5 + 1 25 c ? 4 0 c + 25 c v cm at v cc (2.5v) i b (a) figure 4 . inpu t bias current vs. input common - mode voltage (v) 15 0 1 0 0 5 0 0 o d ( m v ) 6 0 5 5 5 0 4 5 4 0 3 5 3 0 2 5 2 0 propagation delay ( n s ) v cc = 5.5v fall delay v cc = 2.5v rise delay v cc = 5.5v rise delay v cc = 2.5v fall delay 06918-005 figure 5 . propagation delay vs. i nput overdrive at v cc = 2.5 v and 5.5 v 06918-006 1 6 0 1 5 0 1 4 0 1 3 0 1 2 0 1 1 0 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 h y s t e r e s i s ( m v ) 130 0 1 2 0 0 110 0 100 0 90 0 8 0 0 70 0 60 0 5 0 0 40 0 30 0 20 0 10 0 0 h ys r e s i s t o r ( k) v cc = 5.5 v cc = 2.5 figure 6 . hysteresis vs. hys resistor 06918-007 4 . 0 ?1 . 0 ? 0 . 5 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 1 . 5 1 . 0 0 . 5 0 ?0 . 5 ?1 . 0 l o ad cur r e n t ( m a ) s i n k s o urc e v out (v) figure 7 . load current vs. v oh /v ol 06918-008 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 38 . 0 37 . 8 37 . 6 37 . 4 37 . 2 37 . 0 36 . 8 36 . 6 36 . 4 36 . 2 36 . 0 p r o p a g a t io n d e l a y ( n s ) v cm at v cc (2.5v) p r o p a g a t io n d e l a y r i s e p r o p a g a t io n d e l a y f a l l figure 8 . pr opagation delay vs. input common - mode v oltage (v) rev. c | page 6 of 12
data sheet adcmp609 q q 100ns/div 0.5v/div 06918-009 figure 9 . 1 mh z output voltage waveform at v cc = 2.5 v q q 100ns/div 1v/div 06918-010 figure 10 . 1 mh z output vo ltage waveform at v cc = 5.5 v rev. c | page 7 of 12
adcmp609 data sheet application s information power/ground layout and bypassing the adcmp609 comparator is a high speed device. despite the low noise output stage, it is essentia l to use proper high speed design techniques to achieve the specified performance. because comparators are uncompensated amplifiers, feedback in any pha s e relationship is likely to cause oscillations or undesired hysteresis. of critical importance is the u se of low impedance supply planes, particularly the output supply plane (v cc ) and the ground plane. individual supply planes are recommended as part of a multilayer board. providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. it is also important to adequately bypass the input and output supplies. place a 0.1 f bypass capacitor as close as possible to each v cc supply pin. the capacitor should be connected to the ground plane with redundant vias placed to provide a physically short return path for output currents flowing back from ground to the v cc pin. carefully select high frequency bypass capacitors for minimum inductance and effective series resistance (esr) . parasitic layout i nductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. ttl - /cmos- compatible output st age to achieve specified propagation delay performance, keep the capacitive load at or below the specified minimums . the outputs of the adcmp609 are designed to directly drive one schottky ttl or three low power schottky ttl loads ( or an equivalent ) . for large fan outputs, buses, or transmission lines, use an appropriate buffer to maintain th e excellent speed and stability of the comparator . with the rated 1 5 pf load capacitance applied, more than half of the total device propagation delay is output stage slew time . because of this, the total propagation de lay decreases as v cc decreases, and instability in the power supply may appear as excess delay dispersion. d elay is measured to the 50% point for whatever supply is in use; th erefore , the fastest times are observed with the v cc supply at 2.5 v, and larger values are observed when driving loa ds that switch at other levels. overdrive and input slew rate dispersions are not significantly affected by output loading and v cc variations. the ttl - /cmos - compatible output stage is shown in the simplified schematic di agram ( figure 11 ). because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads. output q2 q1 +in ?in output stage v logic gain stage a2 a1 a v 06918-011 figure 11 . sim plified schematic diagram of ttl - /cmos - compatible output stage optimizing performan ce as with any high speed comparator, proper design and layout tech - niques are essential for obtaining the specified performance. stray capacitance, inductance, common powe r and ground impedances, or other layout issues can severely limit performance and often caus e oscillation. the source impedance should be minimize d as much as is practicable. high source impedance, in combination with the parasitic input capacitance of th e comparator, causes an undesirable degradation in bandwidth at the input, th erefore degrading the overall response. higher impedance s encourage undesired coupling. comparator propagati on delay dispersion the adcmp609 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 10 mv to v cc ? 1 v. propagation delay dispersion is the variation in propa - gation delay that results from a change in the degree o f overdri ve or slew rate, which is how far or how fast the input signal exceeds the switching threshold . propagation delay dispersion is a specification that becomes important in high speed, time - critical applications, such as data communication, automatic test and measurement, and instru - mentation. it is also important in event - driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. dispersion is the variation in propagation delay as the input over - drive conditions ar e changed ( see figure 12 and figure 13). adcmp609 dispersion is typically <12 ns as the overdrive varie s from 10 mv to 125 mv. this specification applies to both positive and negative signals because the device has very closely matched delays for both positive - going and negative - going inputs , and very low output sk ews . note that for repeatable dispersion measure - ments t he actu al device offset is added to the overdrive. rev. c | page 8 of 12
data sheet adcmp609 rev. c | page 9 of 12 q/q output input voltage 500mv overdrive 10mv overdrive dispersion v n v os 06918-012 figure 12. propagation delayoverdrive dispersion q/q output input voltage 10v/ns 1v/ns dispersion v n v os 06918-013 figure 13. propagation delayslew rate dispersion comparator hysteresis the addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. the transfer function for a comparator with hysteresis is shown in figure 14. as the input voltage approaches the threshold (0.0 v, in figure 14) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +v h /2. the new switching threshold becomes ?v h /2. the comparator remains in the high state until the threshold, ?v h /2, is crossed from below the threshold region in a negative direction. in this manner, noise or feedback output signals centered on 0.0 v input cannot cause the comparator to switch states unless it exceeds the region bounded by v h /2. output input 0.0v v ol v oh +v h 2 ?v h 2 0 6918-014 figure 14. comparator hysteresis transfer function the customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. one limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. the external feedback network can also introduce significant parasitics that reduce high speed performance and can even induce oscillation in some cases. the adcmp609 comparator offers a programmable hysteresis feature that significantly improves accuracy and stability. connecting an external pull-down resistor or a current source from the hys pin to ground varies the amount of hysteresis in a predictable, stable manner. leaving the hys pin disconnected or driving it high removes the hysteresis. the maximum hysteresis that can be applied using this pin is approximately 160 mv. figure 15 illustrates the amount of hysteresis applied as a function of the external resistor value. 06918-006 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 hysteresis ( m v) 1300120011001000900 800 700600 500400300 200100 0 hys resistor (k ? ) v cc = 5.5 v cc = 2.5 figure 15. hysteresis vs. hys resistor the hys pin appears as a 1.25 v bias voltage seen through a series resistance of 7 k 20% throughout the hysteresis control range. the advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. an external bypass capacitor is not recommended on the hys pin because it impairs the latch function and often degrades the jitter performance of the device. with the pin driven low, hysteresis may become large, but in this device, the effect is not reliable or intended as a latch function. crossover bias point rail-to-rail inputs of this type, in both op amps and comparators, have a dual front-end design. certain devices are active near the v cc rail, and others are active near the v ee rail. at some predeter- mined point in the common-mode range, a crossover occurs. at this point, normally v cc /2, the direction of the bias current reverses and there are changes in measured offset voltages and currents. the adcmp609 slightly elaborates on this scheme. the crossover points are at approximately 0.8 v and 1.6 v.
adcmp609 data sheet minimum input slew r ate requirement with the rated load capacitance and normal good pcb design practice ( as discussed in the optimizing performance section ) , these comparators s hould be stable at any input slew rate with no hysteresis. broadband noise from the input stage is observed in place of the violent chatter seen with most other high speed comparator s. with additional capacitive loading or poor bypassing , o scillation may be encountered . these oscillation s are due to the high gain bandwidth of the comparator in combination with feedback through parasitics in the package and pc b . in many applications, chatter is not harmful. rev. c | page 10 of 12
data sheet adcmp609 typical application s circuits hys adcmp609 5v 150k ? 150k ? control voltage 0v to 2.5v output 39k ? 39k ? 470pf 20k ? 06918-016 figure 16 . voltage controlled oscillator adcmp609 output + ? 5v 0.1f 10k ? 10k ? input v ref 0.02f hys 06918-017 figure 17 . duty cycle to differential voltage converter cmos pwm output adcmp608 2.5v input 1.25v ref input 1.25v 50mv hys adcmp609 220pf 10k ? 10k ? 100k ? 10k ? 06918-018 figure 18 . oscillator and pulse - width modulator rev. c | page 11 of 12
adcmp609 data sheet outline dimensions compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 19 . 8 - lead mini small outline package [msop] (rm - 8) dimensions shown in millimeters o rdering g uide model 1 temperature range package description package option branding adcmp609brmz ?40c to +125c 8-l ead mini small outline package [ msop ] rm -8 gw adcmp609brmz - reel ?40c to +125c 8-l ead mini small outline package [ msop ] rm -8 gw adcmp609brmz - reel7 ?40c to +125c 8-l ead mini small outline package [ msop ] rm -8 gw eval - adcmp609brmz evaluation board 1 z = rohs compliant part. ? 2007 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06918 - 0- 11/14(c) rev. c | page 12 of 12

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